`timescale 1ps / 1ps
module pc(input clk,
          input reset,
          input [31:2]npc,
          output reg [31:2]pc);
    
    initial begin
        pc = 12288;
    end
    
    always @(posedge clk) begin
        pc = npc;
    end
    
    always @(posedge reset) begin
        pc = 12288;//0x000_3000
    end
    
endmodule // pc
